Field effect transistor using carbon nanotubes

ABSTRACT

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including carbon nanotubes (CNTs) embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an interlayer dielectric (ILD) layer is formed over the doped source/drain region and the sacrificial gate structure, a source/drain opening is formed by patterning the ILD layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.

BACKGROUND

As the semiconductor industry has progressed into nanometer technologyprocess nodes in pursuit of higher device density, higher performance,and lower costs, challenges from both fabrication and design issues haveresulted in the development of three-dimensional designs, such as gateall around (GAA) structures. Non-Si based low-dimensional materials arepromising candidates to provide superior electrostatics (e.g., forshort-channel effect) and higher performance (e.g., less surfacescattering). Carbon nanotubes (CNTs) are considered one such promisingcandidate due to their high carrier mobility and substantially onedimensional structure.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A, 1B and 1C show various stages of a sequential fabricationprocess of a GAA FET using a CNT in accordance with an embodiment of thepresent disclosure.

FIGS. 2A, 2B, 2C, 2D and 2E show various stages of a sequentialfabrication process of a GAA FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 2F, 2G, 2H, 2I and 2J show various stages of a sequentialfabrication process of a GAA FET using a CNT in accordance with anembodiment of the present disclosure.

FIG. 3 shows one of the various stages of a sequential fabricationprocess of a GAA FET using a CNT in accordance with an embodiment of thepresent disclosure.

FIG. 4 shows one of the various stages of a sequential fabricationprocess of a GAA FET using a CNT in accordance with an embodiment of thepresent disclosure.

FIG. 5 shows one of the various stages of a sequential fabricationprocess of a GAA FET using a CNT in accordance with an embodiment of thepresent disclosure.

FIGS. 6A and 6B illustrate one of the various stages of a sequentialfabrication process of a GAA FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 7A and 7B illustrate one of the various stages of a sequentialfabrication process of a GAA FET using a CNT in accordance with anembodiment of the present disclosure.

FIG. 8A illustrates one of the various stages of a sequentialfabrication process of a GAA FET using a CNT in accordance with anembodiment of the present disclosure. FIG. 8B illustrates one of thevarious stages of a sequential fabrication process of a GAA FET using aCNT in accordance with another embodiment of the present disclosure.

FIGS. 9A and 9B illustrate one of the various stages of a sequentialfabrication process of a GAA FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 10A and 10B illustrate one of the various stages of a sequentialfabrication process of a GAA FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 11A and 11B illustrate one of the various stages of a sequentialfabrication process of a GAA FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 12A, 12B, 12C, 12D and 12E illustrate one of the various stages ofa sequential fabrication process of a GAA FET using a CNT in accordancewith an embodiment of the present disclosure.

FIGS. 13A and 13B illustrate one of the various stages of a sequentialfabrication process of a GAA FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 14A and 14B illustrate one of the various stages of a sequentialfabrication process of a GAA FET using a CNT in accordance with anembodiment of the present disclosure.

FIG. 15 shows one of the various stages of a sequential fabricationprocess of a GAA FET using a CNT in accordance with another embodimentof the present disclosure.

FIG. 16 shows one of the various stages of a sequential fabricationprocess of a GAA FET using a CNT in accordance with another embodimentof the present disclosure.

FIG. 17 shows one of the various stages of a sequential fabricationprocess of a GAA FET using a CNT in accordance with another embodimentof the present disclosure.

FIG. 18 shows one of the various stages of a sequential fabricationprocess of a GAA FET using a CNT in accordance with another embodimentof the present disclosure.

FIG. 19 shows one of the various stages of a sequential fabricationprocess of a GAA FET using a CNT in accordance with another embodimentof the present disclosure.

FIG. 20 shows one of the various stages of a sequential fabricationprocess of a GAA FET using a CNT in accordance with another embodimentof the present disclosure.

FIG. 21 shows one of the various stages of a sequential fabricationprocess of a GAA FET using a CNT in accordance with another embodimentof the present disclosure.

FIGS. 22A and 22B illustrate one of the various stages of a sequentialfabrication process of an FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 23A and 23B illustrate one of the various stages of a sequentialfabrication process of an FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 24A and 24B illustrate one of the various stages of a sequentialfabrication process of an FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 25A and 25B illustrate one of the various stages of a sequentialfabrication process of an FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 26A and 26B illustrate one of the various stages of a sequentialfabrication process of an FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 27A and 27B illustrate one of the various stages of a sequentialfabrication process of an FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 28A and 28B illustrate one of the various stages of a sequentialfabrication process of an FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 29A and 29B illustrate one of the various stages of a sequentialfabrication process of an FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 30A and 30B illustrate one of the various stages of a sequentialfabrication process of an FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 31A and 31B illustrate one of the various stages of a sequentialfabrication process of an FET using a CNT in accordance with anembodiment of the present disclosure.

FIGS. 32A and 32B show a FET using a CNT in accordance with anotherembodiment of the present disclosure.

FIGS. 33A, 33B, 33C and 33D show simulation results showing doping ofCNTs from a doped bulk semiconductor material.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the invention. Specific embodiments or examples of components andarrangements are described below to simplify the present disclosure.These are, of course, merely examples and are not intended to belimiting. For example, dimensions of elements are not limited to thedisclosed range or values, but may depend upon process conditions and/ordesired properties of the device. Moreover, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed interposing the first and second features, suchthat the first and second features may not be in direct contact. Variousfeatures may be arbitrarily drawn in different scales for simplicity andclarity. In the accompanied drawings, some layers/features may beomitted for simplification.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The device may be otherwise oriented (rotated 90 degrees orat other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. In addition, the term“made of” may mean either “comprising” or “consisting of.” Further, inthe following fabrication process, there may be one or more additionaloperations in/between the described operations, and the order ofoperations may be changed. In the present disclosure, a phrase “one ofA, B and C” means “A, B and/or C” (A, B, C, A and B, A and C, B and C,or A, B and C), and does not mean one element from A, one element from Band one element from C, unless otherwise described. Materials,configurations, dimensions, processes and/or operations same as orsimilar to those described with one embodiment may be employed in theother embodiments and the detailed explanation may be omitted.

Carbon nanotubes (CNTs) having diameters in the order of nm (e.g., about1 nm) are considered a material of choice for making scaled FET devicedue to their cylindrical geometry, excellent electrical and mechanicalproperties. A field effect transistor (FET) using a CNT with a gatelength about 10 nm or less shows excellent electrical characteristics.However, a fabrication technology compatible with a CMOS fabricationtechnology has not been established. In the present disclosure, bystacking layers of aligned CNTs on a substrate and forming a finstructure from the stacked CNTs, a horizontal gate all around processflow compatible with a CMOS technology is provided.

In some embodiments, semiconductor devices include a novel structure offield-effect transistors including stacked, gate-all-around (GAA) carbonnanotubes (CNTs). The semiconductor devices include an array of alignedCNTs with a gate dielectric layer wrapping therearound and a gateelectrode layer. The GAA FETs with CNTs can be applied to logic circuitsin advanced technology node. However, control of the doping profile inCNTs is often challenging. Generally, it is desirable to have an undopedchannel region of the GAA FET, while having doped source/drain extensionand source/drain contact regions.

In the present disclosure, the source/drain region of CNTs is doped froma doped bulk semiconductor material to provide more carriers in the CNTsand to reduce contact resistance.

FIGS. 1A-21 illustrate various stages of a sequential fabricationprocess of a GAA FET using carbon nanotubes in accordance withembodiments of the present disclosure. It is understood that additionaloperations can be provided before, during, and after processes shown byFIGS. 1A-21, and some of the operations described below can be replacedor eliminated, for additional embodiments of the method. The order ofthe operations/processes may be interchangeable.

As shown in FIG. 1A, one or more carbon nanotubes (CNTs) 100 arearranged over a substrate 10. The CNTs are arranged on the substratealigned with substantially the same direction (e.g., Y direction). Thedeviation from the Y direction of the alignment of the CNTs 100 is about±10 degrees in some embodiments, and is about ±5 degrees in otherembodiments. In certain embodiments, the deviation is about ±2 degrees.The CNTs 100 are arranged with a density in a range from about 50tubes/μm to about 300 tubes/μm along the X direction in someembodiments, and in other embodiments, the density is in a range fromabout 100 tubes/μm to about 200 tubes/μm along the X direction. Thelength of the CNTs 100 (in the Y direction) is in a range from about 0.5μm to about 5 μm in some embodiments, and is in a range from about 1 μmto about 2 μm in other embodiments. The average diameter of the CNTs 100is in a range from about 1.0 nm to about 2.0 nm in some embodiments.

In some embodiments, the substrate 10 is made of a suitable elementalcrystalline semiconductor, such as silicon, diamond or germanium; asuitable alloy or compound crystalline semiconductor, such as Group-IVcompound semiconductors (e.g., silicon germanium (SiGe), silicon carbide(SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), GroupIII-V compound semiconductors (e.g., gallium arsenide, indium galliumarsenide (InGaAs), indium arsenide, indium phosphide, indium antimonide,gallium arsenic phosphide, or gallium indium phosphide), or the like. Insome embodiments, crystalline silicon is used as the substrate 10.

In some embodiments, a bottom support layer is formed on the substrate10 and the CNTs 100 are disposed on the bottom support layer. In someembodiments, the bottom support layer includes one or more layers ofsapphire, silicon oxide, silicon nitride, SiON, SiOC, SiOCN and SiCN, orother suitable insulating material. In other embodiments, the bottomsupport layer includes a polycrystalline or amorphous material of one ofSi, Ge and SiGe. The bottom support layer can be formed by suitable filmformation methods, such as thermal oxidation, chemical vapor deposition(CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD).

Carbon nanotubes can be formed by various methods, such as arc-dischargeor laser ablation methods, or a templated CVD method on a sapphiresubstrate. The formed CNTs can be dispersed in a solvent, such as sodiumdodecyl sulfate (SDS). The CNTs can be transferred to and disposed on asubstrate using various methods, such as a floating evaporativeself-assembly method in some embodiments.

FIGS. 2A-2E show operations to transfer the CNTs to the substrate 10. Insome embodiments, CNTs 100 are disposed on a dummy substrate 15 as setforth above and as shown in FIG. 2A. In some embodiments, the dummysubstrate 15 is a sapphire substrate. The CNTs 100 are arranged with apitch in a range from about 5 nm to about 15 nm in some embodiments.Then, a transfer film 17 is formed over the CNTs 100 and the dummysubstrate 15 as shown in FIG. 2B. In some embodiments, the transfer filmis a metal film, such as a gold film. The transfer film 17 is detachedfrom the dummy substrate 15 together with the CNTs 100, as shown in FIG.2C. Then, the transfer film 17 with the CNTs 100 are attached on thesubstrate 10 as shown in FIG. 2D. The transfer film 17 is then detachedfrom the substrate 10, thereby leaving the CNTs 100 on the substrate 10,as shown in FIG. 2E.

In some embodiments, after the CNTs 100 are transferred over thesubstrate 10, a trimming process as shown in FIGS. 2F-2J is performed.After the CNTs 100 are transferred onto the substrate 10 as shown inFIG. 2F (a cross sectional view) and 2G (a top/plan view), a photoresist pattern 12, as a cover layer, is formed over a center part of theCNTs 100 by using a lithography operation. End portions of the CNTs 100are exposed, as shown in FIG. 2H. The width W21 of the photo resistpattern 12 is in a range from about 50 nm to about 2000 nm in someembodiments, and is in a range from about 100 nm to about 1000 nm inother embodiments. Then, the exposed end portions of the CNTs 100 areremoved by etching, as shown in FIG. 2I. Further, as shown in FIG. 2J,the resist pattern 12 is then removed by dry etching and/or wet removalusing an organic solvent. In some embodiments, the trimming process isperformed on the dummy substrate 15 before transferring the CNTs 100 tothe substrate 10.

After the CNTs 100 are transferred onto the substrate 10, a firstsupport layer 21 is formed over the CNTs 100 (a first group of CNTs)disposed on the substrate 10, as shown in FIG. 1B. In some embodiments,the first support layer 21 is made of the same semiconductor material asthe substrate 10 and is epitaxially formed on the substrate 10. In someembodiments, the first support layer 21 is made of a differentsemiconductor material than the substrate 10. In certain embodiments,SiGe is epitaxially formed on the substrate 10. In other embodiments, apolycrystalline or amorphous material of one of Si, Ge and SiGe isformed over the CNTs 100. In certain embodiments, an annealingoperation, such as laser annealing, is performed to crystalize thepolycrystalline or amorphous material layer.

In some embodiments, when the first support layer is conformally formedover the first group of CNTs 100, the upper surface of the first supportlayer has a wavy shape having peaks and valleys. The thickness of thefirst support layer 21 is in a range from about 2 nm to about 20 nm insome embodiments, and is in a range from about 5 nm to 15 nm in otherembodiments. In other embodiments, after the first support layer 21 isformed with the wavy upper surface, one or more planarization operationsare performed to flatten the upper surface of the support layer 21. Theplanarization operation includes an etch-back process or a chemicalmechanical polishing (CMP) process. In one embodiment, CMP is used.

Further, a second group of CNTs 100 are disposed on the first supportlayer 21 as shown in FIG. 1C. Then, a second support layer 22 is formedover the first support layer 21 and the second group of CNTs 100 asshown in FIG. 1C. In some embodiments, the second support layer 22 ismade of the same material as the first support layer 21. In someembodiments, silicon is epitaxially formed over the first support layer22. The thickness of the second support layer 22 is substantially thesame as the thickness of the first support layer 21. The difference inthe thickness is within ±5% in some embodiments with respect to theaverage thickness. Further, a third-sixth group of CNTs 100 are disposedon the second support layer 22 as shown in FIG. 1C.

In some embodiments, forming a group of CNTs and forming a support layerare repeated to form n support layers in each of which CNTs areembedded, where n is integer of two or more, for example 10. In someembodiments, n is up to 20. FIG. 1C shows one embodiment, in which sixsupport layers 21, 22, 23, 24, 25 and 26 are formed, thus forming sixlayers of CNTs disposed in a support layer 20. In the followingexplanation, the first to sixth support layers 21-26 are referred to asa support layer 20.

In FIG. 1C, the CNTs 100 in one layer are arranged in a substantiallyconstant pitch and the CNTs in the vertical direction are aligned.However, the arrangement of the CNTs in the support layer 20 is notlimited to those of FIG. 1C. In some embodiments, the CNTs in one layerhave a random pitch in the X direction. When the average diameter of theCNTs 100 is D_(CNT), horizontal pitch P_(H) of the CNTs isD_(CNT)≤P_(H)≤10×D_(CNT), in some embodiments. In some embodiments, twoadjacent CNTs are in contact with each other. Further, in the verticaldirection, at least two CNTs 100 in different layers are not alignedwith each other, in some embodiments. The vertical pitch P_(V) of theCNTs 100 is determined by the thickness of the support layers. In someembodiments, a vertical pitch P_(V) of the CNTs 100 in adjacent layersis 0.9×P_(A)≤P_(V)≤1.1×P_(A), where P_(A) is an average pitch of themultiple layers. In other embodiments, the vertical pitch P_(V) is0.95×P_(A)≤P_(V)≤1.05×P_(A).

As set forth above, the CNTs 100 are embedded in a crystallinesemiconductor layer 20 over the substrate 10. In some embodiments, eachof the support layers 20 is undoped. In other embodiments, each of thesupport layers 20 is doped.

Adverting to FIG. 3, by using one or more lithography and etchingoperations, a mask pattern 18 is formed over the support layer 20, andthe support layer 20 with the CNTs 100 is patterned into one or more finstructures 30 as shown in FIG. 4. The mask pattern 18 is a photo resistlayer in some embodiments, and is a hard mask made of dielectricmaterial in other embodiments. In some embodiments, the fin structures30 are patterned by any suitable method. For example, the fin structuresmay be patterned using one or more photolithography processes, includingdouble-patterning or multi-patterning processes. Generally,double-patterning or multi-patterning processes combine photolithographyand self-aligned processes, allowing patterns to be created that have,for example, pitches smaller than what is otherwise obtainable using asingle, direct photolithography process. For example, in one embodiment,a sacrificial layer is formed over a substrate and patterned using aphotolithography process. Spacers are formed alongside the patternedsacrificial layer using a self-aligned process. The sacrificial layer isthen removed, and the remaining spacers, or mandrels, may then be usedto pattern the fin structures.

In some embodiments, the width of the fin structures 30 in the Xdirection is in a range from about 5 nm to about 20 nm, and is in arange from about 7 nm to about 12 nm in other embodiments. When thesubstrate 10 is made of the same or similar material as the supportlayers 20, the substrate 10 is also patterned into fin structure asshown in FIG. 4. In other embodiments, when the substrate 10 is made ofa different material than the support layers 20, the substrate 10 is notpatterned.

The total number of the CNTs 100 per fin structure is in a range fromabout 5 to about 100 in some embodiments, and is in a range from about10 about 50 in other embodiments.

Next, as shown in FIG. 5, an isolation insulating layer 15 is formed.The insulating material for the isolation insulating layer 15 mayinclude one or more layers of silicon oxide, silicon nitride, siliconoxynitride (SiON), SiOCN, fluorine-doped silicate glass (FSG), or alow-k dielectric material. The isolation insulating layer is formed byLPCVD (low pressure chemical vapor deposition), plasma-CVD or flowableCVD. In the flowable CVD, flowable dielectric materials instead ofsilicon oxide may be deposited. Flowable dielectric materials, as theirname suggest, can “flow” during deposition to fill gaps or spaces with ahigh aspect ratio. Usually, various chemistries are added tosilicon-containing precursors to allow the deposited film to flow. Insome embodiments, nitrogen hydride bonds are added. Examples of flowabledielectric precursors, particularly flowable silicon oxide precursors,include a silicate, a siloxane, a methyl silsesquioxane (MSQ), ahydrogen silsesquioxane (HSQ), an MSQ/HSQ, a perhydrosilazane (TCPS), aperhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or asilyl-amine, such as trisilylamine (TSA). These flowable silicon oxidematerials are formed in a multiple-operation process. After the flowablefilm is deposited, it is cured and then annealed to remove un-desiredelement(s) to form silicon oxide. When the un-desired element(s) isremoved, the flowable film densifies and shrinks. In some embodiments,multiple anneal processes are conducted. In some embodiments, theflowable film is cured and annealed more than once. The flowable filmmay be doped with boron and/or phosphorous. The insulating layer isfirst formed in a thick layer so that the fin structures 30 are embeddedin the thick layer, and the thick layer is recessed so as to expose theupper portions of the fin structures 30, as shown in FIG. 5. Theinsulating layer can be recessed by using dry and/or wet etching. Afteror before recessing the isolation insulating layer, a thermal process,for example, an anneal process, may be performed to improve the qualityof the isolation insulating layer. In certain embodiments, the thermalprocess is performed by using rapid thermal annealing (RTA) at atemperature in a range from about 900° C. to about 1050° C. for about1.5 seconds to about 10 seconds in an inert gas ambient, such as an N₂,Ar or He ambient.

In some embodiments, the bottommost CNT is located above the uppersurface of the isolation insulating layer 15. In other embodiments, thebottommost CNT is located equal to or below the upper surface of theisolation insulating layer 15.

Subsequently, a sacrificial gate structure 40 is formed over the finstructures 30 as shown in FIGS. 6A and 6B. FIG. 6A is a cross sectionalview along the X direction and the FIG. 6B is a cross sectional viewalong the Y direction. The sacrificial gate structure 40 is formed byblanket depositing a sacrificial gate electrode layer over the finstructures 30 such that the fin structures 30 are fully embedded in thesacrificial gate electrode layer. The sacrificial gate electrode layerincludes polycrystalline or amorphous silicon, germanium or silicongermanium. The thickness of the sacrificial gate electrode layer is in arange from about 100 nm to about 200 nm in some embodiments. In someembodiments, the sacrificial gate electrode layer is subjected to aplanarization operation. The sacrificial gate electrode layer isdeposited using CVD, including LPCVD and PECVD, PVD, ALD, or othersuitable process. In some embodiments, no sacrificial gate dielectriclayer is formed between the fin structure 30 and the sacrificial gateelectrode layer, and in other embodiments, a sacrificial gate dielectriclayer is formed between the fin structure 30 and the sacrificial gateelectrode layer. In some embodiments the sacrificial gate dielectriclayer is silicon dioxide with a thickness between about 1 nm and about 2nm.

Subsequently, a hard mask layer 42 is formed over the sacrificial gateelectrode layer 40. The mask layer 42 includes one or more of a siliconnitride (SiN) layer and a silicon oxide layer, or any other materialsuitable for hard mask. Next, a patterning operation is performed on thehard mask layer and the sacrificial gate electrode layer is patternedinto the sacrificial gate structure 40, as shown in FIGS. 6A and 6B. Bypatterning the sacrificial gate structure, the fin structures 30 arepartially exposed on opposite sides of the sacrificial gate structure40, thereby defining source/drain (S/D) regions, as shown in FIG. 6B. Inthis disclosure, a source and a drain are interchangeably used and thestructures thereof are substantially the same. In FIGS. 6A and 6B, twosacrificial gate structures 40 are formed over two fin structures 30,but the number of the sacrificial gate structures is not limited to thisconfiguration. One or more than two sacrificial gate structures can bearranged in the Y direction in some embodiments. In certain embodiments,one or more dummy sacrificial gate structures are formed on both sidesof the sacrificial gate structures to improve pattern fidelity.

After the sacrificial gate structure 40 is formed, a blanket layer of aninsulating material for gate sidewall spacers 44 is conformally formedby using CVD or other suitable methods, as shown in FIGS. 7A and 7B. Theblanket layer is deposited in a conformal manner so that it is formed tohave substantially equal thicknesses on vertical surfaces, such as thesidewalls, horizontal surfaces, and the top of the sacrificial gatestructures 40. In some embodiments, the blanket layer is deposited to athickness in a range from about 2 nm to about 10 nm. In someembodiments, the insulating material of the blanket layer is a siliconnitride-based material, such as SiN, SiON, SiOCN or SiCN andcombinations thereof. In certain embodiments, the insulating material isone of SiOC, SiCON and SiCN. As understood from FIGS. 7A and 7B, in someembodiments, the CNTs 100 are supported by the support layer 20 but arenot supported (anchored) by the sidewall spacers 44. In someembodiments, before the blanket layer for the sidewall spacers 44 isformed, the support layer 20 is slightly etched to expose the ends ofthe CNTs 100. In such a case, the ends of the CNTs 100 are supported(anchored) by the sidewall spacers 44, and thus ends of the CNTs 100 arecovered by an insulating material.

Further, as shown in FIGS. 7A and 7B, the gate sidewall spacers 44 areformed on opposite sidewalls of the sacrificial gate structures 40 byanisotropic etching. After the blanket layer is formed, anisotropicetching is performed on the blanket layer using, for example, reactiveion etching (RIE). During the anisotropic etching process, most of theinsulating material is removed from horizontal surfaces, leaving thedielectric spacer layer on the vertical surfaces, such as the sidewallsof the sacrificial gate structures and the sidewalls of the exposed finstructures. The mask layer 42 may be exposed from the sidewall spacers44. In some embodiments, an isotropic etching process may besubsequently performed to remove the insulating material from the upperand/or side portions of the S/D region of the exposed fin structures 30.

In some embodiments, the source/drain region of the fin structures 30are ion-implanted to dope impurities in the source/drain regions, toform a doped region 27 as shown in FIG. 8A. In some embodiments, Pand/or As are implanted for an n-type FET and B (BF₂) and/or Ga areimplanted for a p-type FET. In some embodiments, a dose amount iscontrolled such that an impurity concentration in the silicon layer ofthe source/drains is in a range from about 1×10²⁰ atoms/cm³ to about1×10²¹ atoms/cm³. The impurity concentration in the silicon layer of thesource/drains is in a range from about 2×10²⁰ atoms/cm³ to about 5×10²⁰atoms/cm³ in other embodiments.

In other embodiments, a doping layer 38 containing impurities is formedover the source/drain regions of the fin structure 30 as shown in FIG.8B. The doping layer 38 includes Si, SiGe or Ge containing P and/or Asfor an n-type FET and B and/or Ga for a p-type FET by in-situ doping.After the doping layer 38 is formed, a thermal annealing operation isperformed to drive the impurities into the source/drain regions. In someembodiments, the doping layer 38 is removed after the driving-inannealing, and in other embodiments, the doping layer 38 remains.

Subsequently, a liner layer 46, such as an etch stop layer, is formed tocover the gate structures 40 with the sidewall spacer 44 and the exposedfin structures 30. In some embodiments, the liner layer 46 includes asilicon nitride-based material, such as silicon nitride, SiON, SiOCN orSiCN and combinations thereof, formed by CVD, including LPCVD and PECVD,PVD, ALD, or other suitable process. In certain embodiments, the linerlayer 46 is made of silicon nitride. Further, as shown in FIGS. 9A and9B, a first interlayer dielectric (ILD) layer 50 is formed. Thematerials for the first ILD layer 50 include compounds comprising Si, 0,C and/or H, such as silicon oxide, SiCOH and SiOC. Organic materials,such as polymers, may be used for the first ILD layer 50. After thefirst ILD layer 50 is formed, a planarization operation, such as CMP, isperformed, so that the sacrificial gate electrode layer 40 is exposed,as shown in FIGS. 9A and 9B.

As shown in FIGS. 10A and 10B, the sacrificial gate electrode layer 40is then removed, thereby exposing a channel region of the fin structuresin a gate space 55. The sacrificial gate structure 40 can be removedusing plasma dry etching and/or wet etching. When the sacrificial gateelectrode layer 40 is polysilicon and the first ILD layer 50 is siliconoxide, a wet etchant such as a TMAH solution can be used to selectivelyremove the sacrificial gate electrode layer 40.

Further, as shown in FIGS. 11A and 11B, the support layer 20 in the gatespace 55 is removed to release the CNTs 100. The support layer 20 can beremoved selectively to the CNTs 100 using plasma dry etching and/or wetetching. In some embodiments, when the support layer 20 is silicon, thesilicon layer is oxidized into silicon oxide, and the silicon oxide isremoved by appropriate dry and/or wet etching. In some embodiments, asshown in FIG. 11B, part the support layer 20 remains under the sidewallspacer 44.

After the channel regions of the CNTs 100 are released, a gatedielectric layer 102 is formed around the CNTs 100, as shown in FIGS.12A-12D. FIG. 12C is an enlarged view of the gate structure. In someembodiments, the gate dielectric layer 102 includes one or more layersof a dielectric material, such as silicon oxide, silicon nitride, orhigh-k dielectric material, other suitable dielectric material, and/orcombinations thereof. Examples of high-k dielectric material includeHfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminumoxide, titanium oxide, hafnium dioxide-alumina (HfO₂—Al₂O₃) alloy, othersuitable high-k dielectric materials, and/or combinations thereof. Insome embodiments, the gate dielectric layer 102 is made of HfO₂ for ann-channel FET, and is made of Al₂O₃ for a p-channel FET. The gatedielectric layer 102 has a thickness in a range from about 0.5 nm toabout 2.5 nm in some embodiments, and has a thickness in a range fromabout 1.0 nm to about 2.0 nm in other embodiments. The gate dielectriclayer 102 may be formed by CVD, ALD or any suitable method. In oneembodiment, the gate dielectric layer 102 is formed using a highlyconformal deposition process such as ALD in order to ensure theformation of a gate dielectric layer having a uniform thickness aroundeach channel region of the CNTs 100.

In some embodiments, an interfacial layer (not shown) is formed aroundthe CNTs before the gate dielectric layer 102 is formed. The interfaciallayer is made of, for example, SiO₂ and has a thickness in a range fromabout 0.5 nm to about 1.5 nm in some embodiments. In other embodiments,the thickness of the interfacial layer is in a range from about 0.6 nmto about 1.0 nm.

In certain embodiments, one or more work function adjustment layers 104are formed on the gate dielectric layer 102. The work functionadjustment layers 104 are made of a conductive material such as a singlelayer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi orTiAlC, or a multilayer of two or more of these materials. In certainembodiments, TiN is used as the work function adjustment layer 104. Thework function adjustment layer 104 may be formed by ALD, PVD, CVD,e-beam evaporation, or other suitable process. Further, the workfunction adjustment layer 104 may be formed separately for the n-channelFET and the p-channel FET which may use different metal layers. The workfunction adjustment layer 104 has a thickness in a range from about 0.5nm to about 5.0 nm in some embodiments, and has a thickness in a rangefrom about 0.8 nm to about 1.5 nm in other embodiments.

Then, as shown in FIGS. 12A-12D, a gate electrode layer 106 is formedover the work function adjustment layer 104. The gate electrode layer106 includes one or more layers of conductive material, such aspolysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt,molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN,TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials,and/or combinations thereof. The gate electrode layer 106 may be formedby CVD, ALD, electro-plating, or other suitable method. The gateelectrode layer 106 is also deposited over the upper surface of thefirst ILD layer 50, and the gate dielectric layer 102, the work functionadjustment layer 104 and the gate electrode layer 106 formed over thefirst ILD layer 50 are then planarized by using, for example, CMP, untilthe first ILD layer 50 is revealed.

In FIGS. 12A-12D, the gate dielectric layer fully wraps around each ofthe CNTs 100, the work function adjustment layer 104 also fully wrapsaround each of the CNTs 100, and spaces formed between the work functionadjustment layer 104 of adjacent CNTs 100 are filled by the gateelectrode layer 106. In other embodiments, as shown in FIG. 12E, thework function adjustment layer 104 fills spaces between the gatedielectric layer 102 of adjacent CNTs 100, and the gate electrode layer106 covers the outer surface of the work function adjustment layer 104.

In some embodiments, before the gate dielectric layer 102 is formed,insulating inner spacers are formed around the CNTs 100 under thesidewall spacers 44. In some embodiments, an insulating layer isconformally formed inside of the gate space 55 by, for example, ALD orCVD. In some embodiments, the insulating layer is made of silicon oxide,silicon nitride, SiON, SiCN, SiOC, SiOCN or any other suitable material.The insulating layer is then etched to form the insulating inner spacerson ends of the support layers 20 around the CNTs 100 under the sidewallspacers 44.

In some embodiments, as shown in FIG. 12B, part of the support layer 20(semiconductor layer) is disposed between the gate structure and thedoped source/drain region 27. The part of the support layer 20 has alower impurity concentration than the doped region 27.

Then, as shown in FIGS. 13A and 13B, a second ILD layer 60 is formedover the first ILD layer 50, and source/drain contact openings 65 areformed by using one or more lithography and etching operations. FIG. 13Ashows a cross sectional view cutting the source/drain region of the finstructure. In some embodiments, the second ILD layer 60 is patternedsuch that a part of the fin structure is exposed from the second ILDlayer 60 as shown in FIG. 13A. In some embodiments, only the top surfaceof the fin structure is exposed. In other embodiments, about 20% toabout 80% of the height (H1) of fin structure measured from the uppersurface of the isolation insulating layer 15 is exposed, i.e.0.2H1≤H2≤0.8H1, where H2 is the height of the exposed portion. In otherembodiments, substantially the entire fin structure above the isolationinsulating layer 15 is exposed.

Next, as shown in FIGS. 14A and 14B, the source/drain contact openings65 are filled with one or more layers of a conductive material to form asource/drain contact layer 70. The conductive material includes one ormore of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd,Ni, Re, Jr, Ru, Pt, and Zr, or any other suitable conductive materials.

In some embodiments, the source/drain contact layer 70 includes one ormore of TiN, Ti and TaN as a lower layer and one or more of W, Cu and Coas an upper layer. Further, in some embodiments, one or more gatecontacts are formed at the same time as the source/drain contacts or bydifferent operations from the source/drain contacts. In someembodiments, a silicide layer is formed between the fin structure andthe source/drain contact layer 70. The silicide layer includes NiSi,CoSi and WSi in some embodiments.

As shown in FIGS. 14A and 14B, the CNTs include multiple groups of CNTs,separated by support layers. The CNTs in the same group are located at asame height, and the multiple groups are located at different heightsfrom each other.

Subsequently, further CMOS processes are performed to form variousfeatures such as additional interlayer dielectric layers, contacts/vias,interconnect metal layers, and passivation layers, etc.

FIGS. 15-21 illustrate various stages of a sequential fabricationprocess of a GAA FET using a CNT in accordance with another embodimentof the present disclosure. It is understood that additional operationscan be provided before, during, and after processes shown by FIGS.15-21, and some of the operations described below can be replaced oreliminated, for additional embodiments of the method. The order of theoperations/processes may be interchangeable. Materials, configurations,dimensions, processes and/or operations same as or similar to thosedescribed with respect to FIGS. 1A-14B may be employed in the followingembodiments and the detailed explanation may be omitted.

As shown in FIG. 15, a bottom support layer 115 is formed over asubstrate 10. The bottom support layer 115 is made of an insulatingmaterial in some embodiments. In some embodiments, the bottom supportlayer includes one or more layers of silicon oxide, silicon nitride,SiON, SiOC, SiOCN and SiCN, or other suitable insulating material. Inother embodiments, the bottom support layer includes a polycrystallineor amorphous material of one of Si, Ge and SiGe. The bottom supportlayer 115 can be formed by suitable film formation methods, such asthermal oxidation, chemical vapor deposition (CVD), physical vapordeposition (PVD) or atomic layer deposition (ALD). In certainembodiments, silicon oxide (e.g., SiO₂) is used as the bottom supportlayer 115. Then, similar to FIG. 1B, one or more carbon nanotubes (CNTs)100 are arranged over the bottom support layer 115. In some embodiments,the bottom support layer is not used and the CNTs 100 are directlydisposed on the substrate 10.

After the CNTs 100 are disposed onto the bottom support layer 115, afirst support layer 120 is formed over the CNTs (a first group of CNTs)disposed on the bottom support layer 115, as shown in FIG. 15. In someembodiments, the support layer 120 includes a polycrystalline oramorphous material of one of Si, Ge and SiGe. In other embodiments, thesupport layer 120 includes one or more layers of silicon oxide, siliconnitride, SiON, SiOC, SiOCN and SiCN, or other suitable insulatingmaterial. In some embodiments, the support layer 120 includes organicmaterial, such as organic polymers. In certain embodiments, the supportlayer 120 is made of a different material than the bottom support layer115. In other embodiments, the support layer 120 is made of the samematerial as the bottom support layer 115. The support layer 120 can beformed by suitable film formation methods, such as CVD, PVD or ALD. Inone embodiment, ALD is used for its high thickness uniformity andthickness controllability. Disposing CNTs 100 and forming a supportlayer 120 are repeated to form a stacked structure as shown in FIG. 15.

Similar to FIG. 3, by using one or more lithography and etchingoperations, a mask pattern is formed over the support layer 20, and thesupport layer 20 with the CNTs 100 is patterned into one or more finstructures 30 as shown in FIG. 16. In FIG. 16, the bottom support layer115 is made of the same material as or similar material the supportlayers 20 and thus the bottom support layer 115 is also patterned intothe fin structure. When the bottom support layer 115 is made of adifferent material than the support layers 20, the bottom support layer115 may not be patterned.

Subsequently, similar to FIGS. 6A, 6B, 7A, 7B, 9A and 9B, a sacrificialgate structure 40 is formed over the fin structures 30. Subsequently,and gate sidewall spacers 44 are formed. Subsequently, a liner layer 46,such as an etch stop layer, is formed to cover the gate structures 40with the sidewall spacer 44 and the exposed fin structures 30, and afirst interlayer dielectric (ILD) layer 50 is formed. After the firstILD layer 50 is formed, a planarization operation, such as CMP, isperformed, so that the sacrificial gate electrode layer 40 is exposed,as shown in FIG. 17.

Then, as shown in FIG. 18, the sacrificial gate electrode layer 40 isremoved, thereby exposing a channel region of the fin structures in agate space 55. Further, the support layer 20 in the gate space 55 isremoved to release the CNTs 100. After the channel regions of the CNTs100 are released, a gate dielectric layer 102 is formed around the CNTs100, a work function adjustment layer 104 is formed over the gatedielectric layer and a gate electrode layer 106 is formed over the workfunction adjustment layer 104, as shown in FIG. 19.

Then, as shown in FIG. 20, a second ILD layer 60 is formed over thefirst ILD layer 50, and source/drain contact openings 65 are formed byusing one or more lithography and etching operations. By this operation,source/drain regions of the CNTs 100 are exposed in the source/draincontact openings 65. In some embodiments, the source/drain contactopening 65 reaches the substrate 10 as shown in FIG. 20. In someembodiments, as shown in FIG. 12B, a part of the support layer 20remains under the sidewall spacers 44. When the support layer 20 is madeof a dielectric material, the remaining support layer 20 functions asinsulating inner spacers separating the gate electrode layer 106 andsubsequently formed source/drain contact.

Next, as shown in FIG. 21, a semiconductor layer 28 is formed in thesource/drain contact openings 65 to wrap around the CNTs 100. In someembodiments, the semiconductor layer 28 is epitaxially formed over theexposed substrate 10. In some embodiments, the semiconductor layer 28 iscrystalline silicon or SiGe doped with impurities (e.g., in-situdoping), such as P and/or As for an n-type FET and B and/or Ga for ap-type FET. In other embodiments, the semiconductor layer 28 ispolycrystalline or amorphous silicon or SiGe doped with impurities, suchas P and/or As for an n-type FET and B and/or Ga for a p-type FET. Insome embodiments, an impurity concentration in the semiconductor layer28 is in a range from about 1×10²⁰ atoms/cm³ to 1×10²¹ atoms/cm³. Theimpurity concentration in the semiconductor layer 28 is in a range fromabout 2×10²⁰ atoms/cm³ to 5×10²⁰ atoms/cm³ in other embodiments.Further, as shown in FIG. 21, a source/drain contact layer 70 is formedover the semiconductor layer 28. In some embodiments, before forming thesource/drain contact layer 70, an etch-back operation is performed onthe semiconductor layer 28. In some embodiments, before forming thesource/drain contact layer 70, the second and the first ILD layers arepatterned to form a wider source/drain opening, and then thesource/drain opening is filled with the conductive material to form thesource/drain contact layer 70.

Subsequently, further CMOS processes are performed to form variousfeatures such as additional interlayer dielectric layers, contacts/vias,interconnect metal layers, and passivation layers, etc.

FIGS. 22A-31B illustrate various stages of a sequential fabricationprocess of a planar type FET using a CNT in accordance with anotherembodiment of the present disclosure. It is understood that additionaloperations can be provided before, during, and after processes shown byFIGS. 22A-31B, and some of the operations described below can bereplaced or eliminated, for additional embodiments of the method. Theorder of the operations/processes may be interchangeable. Materials,configurations, dimensions, processes and/or operations same as orsimilar to those described with respect to FIGS. 1A-21 may be employedin the following embodiments and the detailed explanation may beomitted. In FIGS. 22A-31B, the “A” figures are cross sectional viewsalong the gate extending direction (X) in a source/drain region and the“B” figures are cross sectional views along the source-to-draindirection (Y) under the gate.

As shown in FIGS. 22A and 22B, a bottom support layer 13 is formed overa substrate 10. The bottom support layer 13 is made of an insulatingmaterial in some embodiments. In some embodiments, the bottom supportlayer includes one or more layers of silicon oxide, silicon nitride,SiON, SiOC, SiOCN and SiCN, or other suitable insulating material. Thebottom support layer 13 can be formed by suitable film formationmethods, such as thermal oxidation, CVD, PVD or ALD. In certainembodiments, silicon oxide (e.g., SiO₂) is used as the bottom supportlayer 13. After the CNTs 100 are disposed onto the bottom support layer13, a sacrificial gate structure 40 is formed over the CNTs 100, andthen, gate sidewall spacers 44 are formed, as shown in FIGS. 23A and23B. In some embodiments, CNT trimming operations are performed toadjust the number of the CNTs and/or length of the CNTs.

Subsequently, a first interlayer dielectric (ILD) layer 50 is formed, asshown in FIGS. 24A and 24B. After the first ILD layer 50 is formed, aplanarization operation, such as CMP, is performed, so that thesacrificial gate electrode layer 40 is exposed, as shown in FIGS. 25Aand 25B.

Then, the sacrificial gate electrode layer 40 is removed, therebyexposing a channel region of the CNTs 100. After the channel regions ofthe CNTs 100 are released, a gate dielectric layer 102 is formed around(but not fully surrounding) the CNTs 100, a work function adjustmentlayer 104 is formed over the gate dielectric layer and a gate electrodelayer 106 is formed over the work function adjustment layer 104, asshown in FIGS. 26A and 26B.

Then, as shown in FIGS. 27A and 27B, a second ILD layer 60 is formedover the first ILD layer 50, and source/drain contact openings 65 areformed by using one or more lithography and etching operations as shownin FIGS. 28A and 28B. By this operation, source/drain regions of theCNTs 100 are exposed in the source/drain contact openings 65. In someembodiments, as shown in FIGS. 28A and 28B, a part of the bottom supportlayer 12 remains.

Next, as shown in FIGS. 29A and 29B, a semiconductor layer 128 is formedin the source/drain contact openings 65 to wrap around the CNTs 100. Insome embodiments, the semiconductor layer 128 is polycrystalline oramorphous silicon or SiGe doped with impurities, such as P and/or As foran n-type FET and B and/or Ga for a p-type FET. In some embodiments, animpurity concentration in the semiconductor layer 128 is in a range fromabout 1×10²⁰ atoms/cm³ to 1×10²¹ atoms/cm³. The impurity concentrationin the semiconductor layer 128 is in a range from about 2×10²⁰ atoms/cm³to 5×10²⁰ atoms/cm³ in other embodiments. Further, as shown in FIGS. 29Aand 29B, a source/drain contact layer 70 is formed over thesemiconductor layer 128. In some embodiments, before forming thesource/drain contact layer 70, an etch-back operation is performed onthe semiconductor layer 128.

In some embodiments, as shown in FIGS. 30A and 30B, when thesource/drain contact opening 65 is formed, the substrate 10 is exposed.The semiconductor layer 128 is epitaxially formed over the exposedsubstrate 10 as shown in FIGS. 31A and 31B. In some embodiments, thesemiconductor layer 128 is crystalline silicon or SiGe doped withimpurities, such as P and/or As for an n-type FET and B and/or Ga for ap-type FET.

Subsequently, further CMOS processes are performed to form variousfeatures such as additional interlayer dielectric layers, contacts/vias,interconnect metal layers, and passivation layers, etc.

FIGS. 32A and 32B show a FET using a CNT in accordance with anotherembodiment of the present disclosure. Materials, configurations,dimensions, processes and/or operations same as or similar to thosedescribed with respect to FIGS. 1A-31B may be employed in the followingembodiments and the detailed explanation may be omitted. In theseembodiments, the CNTs 100 form a network. In some embodiments, the CNTs100 are randomly disposed over the support layer 13 vertically andhorizontally.

FIGS. 33A-33D show simulation results of doping to CNTs from a dopedbulk semiconductor material.

FIG. 33A shows a simulation model of a source/drain region of a CNT FET.The simulated CNT has a diameter of 1 nm and has a band gap about 0.8eV, and is embedded in n⁺-doped Si. A conduction band offset between Siand CNT is assumed 0.1 eV. FIGS. 33B and 33C show conduction band energywith respect to the distance r from the center of the CNT. FIG. 33B isthe case where a doping concentration in Si is 1×10²⁰ atoms/cm³ and FIG.33C is the case where a doping concentration in Si 2×10²⁰ atoms/cm³. Thecarrier density in the CNT is 0.44 per nm in FIG. 33B and 0.57 per nm inFIG. 33C. Further, as shown in FIG. 33D, increasing of doping amount inSi increases carrier density in CNT. The simulated results show that thesource/drain structure of a CNT FET according to the present embodimentsinduce sufficient carriers in the CNT.

It will be understood that not all advantages have been necessarilydiscussed herein, no particular advantage is required for allembodiments or examples, and other embodiments or examples may offerdifferent advantages. For example, in the present disclosure, becausestacked structures of CNTs are formed as fin structures, it is possibleto increase CNT density within one GAA FET. Further, by utilizing thedoped semiconductor layer (e.g., n⁺-Si) in the source/drain regions ofthe CNT, it is possible to increase movable carriers in the source/drainregions and to reduce contact resistance in the source/drain regions.

In accordance with an aspect of the present disclosure, in a method offorming a gate-all-around field effect transistor (GAA FET), a finstructure including CNTs embedded in a semiconductor layer is formed, asacrificial gate structure is formed over the fin structure, thesemiconductor layer is doped at a source/drain region of the finstructure, an interlayer dielectric (ILD) layer is formed, asource/drain opening is formed by patterning the ILD layer, and asource/drain contact layer is formed over the doped source/drain regionof the fin structure. In one or more of the foregoing and followingembodiments, the semiconductor layer is crystalline silicon. In one ormore of the foregoing and following embodiments, an impurityconcentration in the semiconductor layer after the doping is in a rangefrom 1×10²⁰ atoms/cm³ to 1×10²¹ atoms/cm³. In one or more of theforegoing and following embodiments, the semiconductor layer is doped byion implantation. In one or more of the foregoing and followingembodiments, doping the semiconductor layer is includes forming a dopinglayer containing impurities over the source/drain region, and drivingthe impurities into the source/drain region by a thermal operation. Inone or more of the foregoing and following embodiments, thesemiconductor layer is poly crystalline or amorphous. In one or more ofthe foregoing and following embodiments, the fin structure is formed by:(i) disposing a group of CNTs over a substrate, (ii) forming anepitaxial semiconductor layer to cover the CNTs, (iii) repeating (i) and(ii) for 2 to 10 times to form a stacked structure, and (iv) patterningthe stacked structure by one or more lithography and etching operations.In one or more of the foregoing and following embodiments, the epitaxialsemiconductor layer is made of a same material as the substrate. In oneor more of the foregoing and following embodiments, a thickness of theepitaxial semiconductor layer is in a range from 5 nm to 15 nm. In oneor more of the foregoing and following embodiments, in forming thesource/drain opening, 20% to 80% of a height of the fin structure isexposed in the source/drain opening.

In accordance with another aspect of the present disclosure, in a methodof forming GAA FET, a fin structure, in which carbon nanotubes (CNTs)are embedded in a support material, is formed over a substrate, asacrificial gate structure is formed over the fin structure, aninsulating layer is formed over the sacrificial gate structure and thefin structure, the sacrificial gate structure is removed so that a partof the fin structure is exposed, the support material is removed fromthe exposed part of the fin structure so that channel regions of CNTsare exposed, a gate structure is formed around the exposed channelregions of CNTs, a source/drain opening is formed in the insulatinglayer, the support material in the source/drain opening is removed sothat source/drain regions of the CNTs are exposed, a semiconductor layeris formed around the exposed CNTs in the source/drain opening, and asource/drain contact layer is formed over the semiconductor layer. Inone or more of the foregoing and following embodiments, after thesource/drain opening is formed, a part of the substrate is exposed inthe source/drain opening. In one or more of the foregoing and followingembodiments, the semiconductor layer is crystalline silicon epitaxiallyformed on the exposed substrate. In one or more of the foregoing andfollowing embodiments, after the source/drain opening is formed, adielectric layer is disposed between the substrate and a bottom of thesource/drain opening so that the substrate is not exposed. In one ormore of the foregoing and following embodiments, the semiconductor layeris poly crystalline or amorphous. In one or more of the foregoing andfollowing embodiments, an impurity concentration in the semiconductorlayer is in a range from 2×10²⁰ atoms/cm³ to 5×10²⁰ atoms/cm³.

In accordance with another aspect of the present disclosure, in a methodof forming a field effect transistor, a carbon nanotube (CNT) isdisposed on a support layer, a sacrificial gate structure is formed overthe CNT, an insulating layer is formed over the sacrificial gatestructure and the CNT, the sacrificial gate structure is replaced with ametal gate structure, a source/drain opening is formed in the insulatinglayer, a semiconductor layer is formed around the exposed CNTs in thesource/drain opening, and a source/drain contact layer is formed overthe semiconductor layer. In one or more of the foregoing and followingembodiments, after the source/drain opening is formed, a part of thesubstrate is exposed in the source/drain opening. In one or more of theforegoing and following embodiments, the semiconductor layer iscrystalline silicon epitaxially formed on the exposed substrate. In oneor more of the foregoing and following embodiments, after thesource/drain opening is formed, a dielectric layer is disposed betweenthe substrate and a bottom of the source/drain opening so that thesubstrate is not exposed.

In accordance with one aspect of the present disclosure, a semiconductordevice having a GAA FET includes carbon nanotubes (CNTs) disposed over asubstrate, a gate structure formed around each of the CNTs in a channelregion, a doped semiconductor layer wrapping around each of the CNTs ina source/drain region, and a source/drain contact formed over thesemiconductor layer. In one or more of the foregoing and followingembodiments, the doped semiconductor layer is crystalline silicon dopedwith impurities. In one or more of the foregoing and followingembodiments, an impurity concentration in the doped semiconductor layeris in a range from 1×10²⁰ atoms/cm³ to 1×10²¹ atoms/cm³. In one or moreof the foregoing and following embodiments, the GAA FET is an n-type FETand the doped semiconductor layer contains at least one of P and As asimpurities. In one or more of the foregoing and following embodiments,the GAA FET is a p-type FET and the doped semiconductor layer containsat least one of B and Ga as impurities. In one or more of the foregoingand following embodiments, a semiconductor layer having a lower impurityconcentration than the doped semiconductor layer is disposed between thedoped semiconductor layer and the gate structure. In one or more of theforegoing and following embodiments, the CNTs include multiple groups ofCNTs, the CNTs in a same group are located at a same height, and themultiple groups are located at different heights from each other. In oneor more of the foregoing and following embodiments, one group isseparated from an adjacent group by a distance in a range from 5 nm to15 nm. In one or more of the foregoing and following embodiments, thedoped semiconductor layer and the substrate are made of one of Si andSiGe. In one or more of the foregoing and following embodiments, ends ofthe CNTs are covered by a dielectric material.

In accordance with another aspect of the present disclosure, asemiconductor device having a field effect transistor includes anisolation insulating layer disposed over a substrate, carbon nanotubes(CNTs) disposed over the substrate, a gate structure formed around eachof the CNTs in a channel region, a doped semiconductor layer wrappingaround each of the CNTs in a source/drain region, and a source/draincontact formed over the semiconductor layer. The doped semiconductorlayer is in contact with the isolation insulating layer. In one or moreof the foregoing and following embodiments, the doped semiconductorlayer passes through the isolation insulating layer and is in contactwith the substrate. In one or more of the foregoing and followingembodiments, the doped semiconductor layer is not in contact with thesubstrate. In one or more of the foregoing and following embodiments,the gate structure includes a gate dielectric layer wrapping around eachof the CNTs, a work function adjustment layer formed on the gatedielectric layer and a gate electrode layer formed on the work functionadjustment layer. In one or more of the foregoing and followingembodiments, the work function adjustment layer partially wraps aroundthe CNTs with the gate dielectric layer. In one or more of the foregoingand following embodiments, the work function adjustment layer fullywraps around each of the CNTs with the gate dielectric layer. In one ormore of the foregoing and following embodiments, the gate dielectriclayer includes one selected from the group consisting of HfO₂ and Al₂O₃.In one or more of the foregoing and following embodiments, the workfunction adjustment layer includes TiN. In one or more of the foregoingand following embodiments, the doped semiconductor layer is made ofSiGe.

In accordance with another aspect of the present disclosure, asemiconductor device having a GAA FET includes a first GAA FET, and asecond GAA FET. Each of the first GAA FET and the second GAA FETincludes carbon nanotubes (CNTs) disposed over a substrate, and a gatestructure formed around the CNTs in a channel region. The CNTs areshared by the first GAA FET and the second GAA FET, and source/drainregions of the CNTs are wrapped around by a doped silicon layer.

The entire disclosure of U.S. patent application Ser. No. 16/120,158 areincorporated herein by reference.

The foregoing outlines features of several embodiments or examples sothat those skilled in the art may better understand the aspects of thepresent disclosure. Those skilled in the art should appreciate that theymay readily use the present disclosure as a basis for designing ormodifying other processes and structures for carrying out the samepurposes and/or achieving the same advantages of the embodiments orexamples introduced herein. Those skilled in the art should also realizethat such equivalent constructions do not depart from the spirit andscope of the present disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

What is claimed is:
 1. A method of forming a gate-all-around fieldeffect transistor (GAA FET), the method comprising: forming a finstructure including carbon nanotubes (CNTs) embedded in a semiconductorlayer; forming a sacrificial gate structure over the fin structure;forming a doped source/drain region by doping the semiconductor layer ata source/drain region of the fin structure; forming an interlayerdielectric (ILD) layer over the doped source/drain region and thesacrificial gate structure; forming a source/drain opening by patterningthe ILD layer; and forming a source/drain contact layer over the dopedsource/drain region of the fin structure.
 2. The method of claim 1,wherein the semiconductor layer is crystalline silicon.
 3. The method ofclaim 1, wherein an impurity concentration in the semiconductor layerafter the doping is in a range from 1×10²⁰ atoms/cm³ to about 1×10²¹atoms/cm³.
 4. The method of claim 1, wherein the semiconductor layer isdoped by ion implantation.
 5. The method of claim 1, wherein the dopingthe semiconductor layer comprises: forming a doping layer containingimpurities over the source/drain region; and driving the impurities intothe source/drain region by a thermal operation.
 6. The method of claim1, wherein the semiconductor layer is poly crystalline or amorphous. 7.The method of claim 1, wherein the fin structure is formed by: (i)disposing a group of CNTs over a substrate; (ii) forming an epitaxialsemiconductor layer to cover the CNTs; (iii) repeating (i) and (ii) for2 to 10 times to form a stacked structure; and (iv) patterning thestacked structure by one or more lithography and etching operations. 8.The method of claim 7, wherein the epitaxial semiconductor layer is madeof a same material as the substrate.
 9. The method of claim 7, wherein athickness of the epitaxial semiconductor layer is in a range from 5 nmto 15 nm.
 10. The method of claim 1, wherein in forming the source/drainopening, 20% to 80% of a height of the fin structure is exposed in thesource/drain opening.
 11. A method of forming a gate-all-around fieldeffect transistor (GAA FET), the method comprising: forming a finstructure, in which carbon nanotubes (CNTs) are embedded in a supportmaterial, over a substrate; forming a sacrificial gate structure overthe fin structure; forming an insulating layer over the sacrificial gatestructure and the fin structure; removing the sacrificial gate structureso that a part of the fin structure is exposed to form an exposed partof the fin structure; removing the support material from the exposedpart of the fin structure so that channel regions of CNTs are exposed toform exposed channel regions of CNTs; forming a gate structure aroundthe exposed channel regions of CNTs; forming a source/drain opening inthe insulating layer; removing the support material in the source/drainopening so that source/drain regions of the CNTs are exposed to formexposed CNTs; forming a semiconductor layer around the exposed CNTs inthe source/drain opening; and forming a source/drain contact layer overthe semiconductor layer.
 12. The method of claim 11, wherein after thesource/drain opening is formed, a part of the substrate is exposed inthe source/drain opening.
 13. The method of claim 12, wherein thesemiconductor layer is crystalline silicon epitaxially formed on theexposed substrate.
 14. The method of claim 11, wherein after thesource/drain opening is formed, a dielectric layer is disposed betweenthe substrate and a bottom of the source/drain opening so that thesubstrate is not exposed.
 15. The method of claim 14, wherein thesemiconductor layer is poly crystalline or amorphous.
 16. The method ofclaim 11, wherein an impurity concentration in the semiconductor layeris in a range from 2×10²⁰ atoms/cm³ to about 5×10²⁰ atoms/cm³.
 17. Amethod of forming a field effect transistor, the method comprising:disposing a carbon nanotube (CNT) on a support layer disposed over asubstrate; forming a sacrificial gate structure over the CNT; forming aninsulating layer over the sacrificial gate structure and the CNT;replacing the sacrificial gate structure with a metal gate structure;forming exposed CNTs by forming a source/drain opening in the insulatinglayer; forming a semiconductor layer around the exposed CNTs in thesource/drain opening; and forming a source/drain contact layer over thesemiconductor layer.
 18. The method of claim 17, wherein after thesource/drain opening is formed, a part of the substrate is exposed inthe source/drain opening.
 19. The method of claim 18, wherein thesemiconductor layer is crystalline silicon epitaxially formed on thepart of the substrate.
 20. The method of claim 18, wherein after thesource/drain opening is formed, an insulating layer is disposed betweenthe substrate and a bottom of the source/drain opening so that thesubstrate is not exposed.